This invention relates generally to frequency synthesizers, and more particularly to modulation of a frequency synthesizer.
Frequency divider circuits are used in frequency synthesizers, and more particularly to modulation of a frequency synthesizer.
Frequency divider circuits are used in frequency synthesizer circuits such as in phase locked loop (PLL). IN a PLL circuit, the output frequency (fo) of a voltage controlled oscillator (VCO) is divided (56') and applied to a phase detector. The phase detector operates to compare the phase of the divided output signal with a reference frequency (f.sub.r) from a reference oscillator in order to control the VCO output frequency. The output frequency (fo) is related to the reference frequency of the reference oscillator by the relationship fo =M x f.sub.r, where M is a divider modulus code which determines the extent that the output frequency is divided before it is compared with the reference frequency. As is known, M may be produced by a signal processor.
One direction in frequency synthesizer design is towards improving the performance of PLL frequency synthesizers by widening the loop bandwidth. A wider loop bandwidth improves transient response and reduces noise better than a narrow loop bandwidth. However, a wider loop bandwidth requires a higher reference frequency with a resultant lower divider modulus (M). As the modulus is decreased, the phase excursion required at a phase modulator (which is typically coupled to one input of the phase detector) for conventional frequency modulation may increase beyond a limit (i.e., the modulator's linear operating range of II radians). This problem is intensified with low frequency modulating signals, which require an even greater phase excursion. Therefore, a need exists to increase the maximum amount of phase excursion to facilitate modulation via a low frequency modulating signal in a PLL having a high reference frequency.